This disclosure relates to a phase interpolator that interpolates between phases of a plurality of differential input signals to produces a differential output signal having a desired phase.
FIG. 12 shows a circuit diagram of an conventional phase interpolator. The phase interpolator 32 shown in FIG. 12 receives input signals I, Q, Ib, and Qb, which are four-phase signals that are 90° out of phase from each other. That is, the phase interpolator 32 divides a full cycle of a reference clock signal into first to fourth quadrants with the input signals I, Ib, Q, and Qb, as shown in FIG. 13. The phase interpolator 32 interpolates between the phases of these input signals.
The phase interpolator 32 includes four differential pairs 12-1 to 12-4, sixteen current sources 14-1 to 14-16, a group of switches 16 composed of a plurality of switches, and two load resistors 18A and 18B. Each of the differential pairs 12-1 to 12-4 includes two NMOSs (N-channel metal-oxide semiconductor transistors) 20A and 20B.
The NMOSs 20A of the differential pairs 12-1 to 12-4 are commonly connected to form a negative output node N, which is connected to the power supply through a load resistor 18A. The NMOSs 20B of the differential pairs 12-1 to 12-4 are commonly connected to form a positive output node P, which is connected to the power supply through a load resistor 18B. The phase interpolator 32 outputs a differential output signal OUTP and OUTN having a desired phase from the positive and negative output nodes.
As shown in FIG. 14, the input signals I, Ib, Q, and Qb are four-phase signals having sine waveforms or near sine waveforms and they are assumed to have the same amplitude. The input signals have phases that are 90° out of phase from each other in the order of the input signals I, Q, Ib, and Qb. For example, the input signals I, Q, Ib, and Qb have phases of 0°, 90°, 180°, and 270°, respectively.
The group of switches 16 includes four quadrant switching switches 22-1 to 22-4 and sixteen pairs of phase switching switches 24-1N and 24-1P to 24-16N and 24-16P. A control code is supplied to the group of switches 16 to select one of the quadrants and to select the phase within the selected quadrant. That is, the control code includes a quadrant switching signal to control the quadrant switching switches 22-1 to 22-4, and a phase switching signal to control the phase switching switches 24-1N and 24-1P to 24-16N and 24-16P.
In the first quadrant, the quadrant switching switches 22-1 and 22-3 are turned on in accordance with the quadrant switching signal, and the differential pairs 12-1 and 12-3 are selected. The phase switching switches 24-1N and 24-1P to 24-16N and 24-16P are turned on or off in accordance with the phase switching signal, and the numbers of current sources connected to each of the differential pairs 12-1 and 12-3 are determined. Specifically, in each of the pairs of switches 24-iN and 24-iP, where i=1 to 16, one of the switches is turned on and the other is turned off in accordance with the phase switching signal.
For example, the phase switching signal may be set such that the phase switching switch 24-1N is turned on, the phase switching switch 24-1P is turned off, the phase switching switches 24-2N to 24-16N are turned off, and the phase switching switches 24-2P to 24-16P are turned on. In this case, one current source 14-1 becomes connected to the source coupled node S, or a connection node of sources of NMOS 20A and NMOS 20B, of the differential pair 12-1. Fifteen current sources 14-2 to 14-16 become connected to the source coupled node S of the differential pair 12-3.
On or off state of each of NMOSs 20A and 20B of the differential pair 12-1 varies in accordance with the differential input signal I and Ib. The current supplied from the current source 14-1 is divided and flows through the NMOSs 20A and 20B of the differential pair 12-1 with varying ratios in accordance with the on or off states of each of the NMOSs 20A and 20B. Similarly, on or off state of each of NMOSs 20A and 20B of the differential pair 12-3 varies in accordance with the differential input signal Q and Qb. A sum of currents supplied from the current sources 14-2 to 14-16 is divided and flows through the NMOSs 20A and 20B of the differential pair 12-3 with varying ratios in accordance with the on or off state of each of the NMOSs 20A and 20B.
The currents that flow through NMOSs 20A of the differential pairs 12-1 and 12-3 are combined and summed at the negative output node N. The currents that flow through NMOSs 20B of the differential pairs 12-1 and 12-3 are combined and summed at the positive output node P. The combined currents further flow through respective load resistors 18A and 18B and are converted to the differential output signal OUTN and OUTP.
That is, phase interpolator 32 combines the input signals I and Q with a ratio corresponding to the ratio between the currents supplied to the source coupled nodes of the differential pairs 12-1 and 12-3 to generate the differential output signal OUTP and OUTN. The control code, which controls the ratio of currents supplied to the differential pairs 12-1 and 12-3, controls the phase of the differential output signal.
Phase of the differential output signal OUTP and OUTN in the first quadrant can be switched with a predetermined interval, or a phase step, by switching the phase switching switches 24-1N and 24-1P to 24-16N and 24-16P in accordance with the control code. The same applies to the second to fourth quadrants. The differential output signal OUTP and OUTN having phases in the range of 0° to 90° for the first quadrant, in the range of 90° to 180° for the second quadrant, in the range of 180° to 270° for the third quadrant, and in the range of 270° to 360° for the fourth quadrant are generated.
As shown in FIG. 12, the phase interpolator 32 includes sixteen current sources 14-1 to 14-16 arranged in parallel. If each of the sixteen current sources 14-1 to 14-16 supplies the same current, the phase interpolator 32 can vary the phase of the differential output signal OUTP and OUTN in sixteen steps in each of the quadrants.
That is, the combination of four quadrant switching switches 22-1 to 22-4 and sixteen pairs of phase switching switches 24-1N and 24-1P to 24-16N and 24-16P enables to vary the phase of differential output signal OUTP and OUTN in 64 steps by using sixteen current sources. In this example, a shared use of the current sources in the first to fourth quadrants enables to decrease the number of current sources to 16, which is one-quarter of the number of steps.
Various references disclose phase interpolators with various other constructions. For example, Japanese Patent No. 3880302 (Patent Document 1) discloses a phase interpolator in witch one variable current source is provided for each of the differential pairs. In the phase interpolator disclosed in Patent Document 1, each of the variable current sources has a capacity of supplying the maximum current that the corresponding differential pair requires. That is, each of the variable current sources has a capacity of supplying the total current that the sixteen currents sources 14-1 to 14-16 in the phase interpolator 32 shown in FIG. 12 supply.
As a result, the phase interpolator disclosed in the Patent Document 1 requires four time larger total current supply capacity, and requires larger total area for providing current sources. Thus, the phase interpolator 32 shown in FIG. 12 is advantageous in that it requires less area for proving current sources.
However, the phase interpolator 32 shown in FIG. 12 utilizes the group of switches 16 including the quadrant switching switches 22-1 to 22-4 and the phase switching switches 24-1N and 24-1P to 24-16N and 24-16P to supply currents from the current sources 14-1 to 14-16 to the source coupled nodes of the differential pairs 12-1 to 12-4. Accordingly, a parasitic capacitance including those of the switches, the current sources, and wirings between the differential pairs and the current sources is connected to the source coupled nodes of the differential pairs selected by the quadrant switching switches.
The parasitic capacitance affects the phase of differential output signal OUTP and OUTN, which is supposed to be determined only by the ratio of currents supplied to the source coupled nodes of the differential pairs. As a result, the phase interpolator shown in FIG. 12 has a problem that the phase error is large.
The problem of the phase error could be solved if the current supplied from the current sources 14-1 to 14-16 were sufficiently larger than the current flowing through the parasitic capacitance. In actual, however, the current sources 14-1 to 14-16 are usually designed to have a minimal size in order to reduce the circuit area. Accordingly, the current supplied from the current sources 14-1 to 14-16 cannot always be sufficiently larger than the current flowing through the parasitic capacitance.
The parasitic capacitance connected to the source coupled node varies depending on connection patterns, or on or off states of the switches, of the group of switches 16. That is, the parasitic capacitance is a function of the control code and increases when the control code has a specific value. Furthermore, the phase error resulting from the parasitic capacitance varies widely depending on the input conditions of the differential input signals to the phase interpolator 32 or the PVT conditions, which includes fabrication process of the semiconductor integrated circuit that includes the phase interpolator, power supply voltage of the phase interpolator, and operating temperature of the phase interpolator. Thus, it is virtually impossible to cancel out the phase error by adjusting the sizes of transistors or other parameters.